Hardware Architecture & Pinout Reference
Demystifying the internal RDA8951G silicon, PCB component blocks, RF antenna paths, and providing schematic-verified pinout tables with corrected header numbering.
BLUF: Bottom Line Up Front
The AI-Thinker A7 module is powered by the RDA Microelectronics RDA8951G baseband processor. The GPS receiver is built directly into the RDA8951G silicon—there is no standalone GPS chip and no external GPS_RX pin. The module outputs 9600-baud NMEA sentences exclusively on GPS_TXD (Header P1 Pin 11).
Critical Pinout Warning: Many early handwritten user diagrams inverted the pin numbering on Header P2. The verified pin layout places Pin 1 at REC+ (top), Pin 11 at PWR_KEY, and Pin 12 at VCC4.0 / VBAT (bottom).
1. Silicon Architecture: The RDA8951G Inside
Under the RF shield of the AI-Thinker A7 sits the RDA8951G System-on-Chip (SoC) manufactured by RDA Microelectronics (Unisoc). Unlike standalone GPS modules (such as the u-blox NEO-6M or MediaTek MTK3339) that feature independent microcontrollers and bidirectional serial ports (TX + RX), the GPS engine inside the A7 is an internal peripheral block.
Baseband Core
32-bit ARM RISC core running RDA’s proprietary real-time cellular RTOS with integrated power management.
Cellular Subsystem
Quad-Band GSM/GPRS (850/900/1800/1900 MHz), GPRS Class 10 (85.6 kbps downlink, 42.8 kbps uplink).
Navigation Engine
Integrated high-sensitivity GPS/GLONASS core. Controlled internally via AT commands on the primary UART; outputs raw NMEA on GPS_TXD.
2. Breakout Board Hardware Subsystems
The standard blue/black AI-Thinker A7 Core Development Board (dimensions: 50.0mm × 36.5mm) provides several essential power and signal-conditioning blocks:
+-------------------------------------------------------------------------+
| [DC Barrel Jack] [Slide SW] [u.FL: GSM] [u.FL: GPS] |
| (5V-9V Input) |
| |
| +-----------+ +---------+ +-------------------------------+ |
| | MP1584 | | K1 | | | |
| | 3A Buck | | (POWER) | | AI-THINKER A7 | |
| | Converter | +---------+ | MODULE | |
| +-----------+ | (RDA8951G) | |
| [Inductor] [LED1] [LED2] | | |
| 10uH / 3A (NET) (GPS) | | |
| +-------------------------------+ |
| +-----------+ [470uF Cap] |
| | SP3232 | (TDMA Buffer) |
| | RS232 IC | [Self-ejecting Micro-SIM Slot] |
| +-----------+ |
| [3.5mm Audio] |
| |
| P1 Header (12 Pins: Left) P2 Header (12 Pins: Right) |
| [1] EN [1] REC+ |
| [2] VCC4.0 / VBAT [2] REC- |
| [3] GND [3] MIC+ |
| [4] U_RXD [4] MIC- |
| [5] U_TXD [5] RESET |
| [6] GND [6] U_RTS |
| [7] HST_TXD [7] U_CTS |
| [8] HST_RXD [8] SLEEP |
| [9] RS232_TXD [9] GND |
| [10] RS232_RXD [10] GND |
| [11] GPS_TXD [11] PWR_KEY |
| [12] GND [12] VCC4.0 / VBAT |
+-------------------------------------------------------------------------+- MP1584 High-Frequency Step-Down Regulator (U1): Steps down 5V–9V DC from the barrel jack to 4.0V DC at up to 3A peak.
- Bulk 470µF Capacitor (C1): Buffers the 4.0V rail during the 2.0A GSM TDMA transmission pulses.
- Sipex SP3232 / MAX232 Transceiver (U5): Provides true RS-232 level shifting for legacy DB9 cables. Warning: Hard-wired to
U_RXD, creating a bus collision hazard (see Chapter 3). - Push-Push Micro-SIM Socket: Includes SMF05C TVS protection diode array against electrostatic discharge.
- 3.5mm Headset Jack (PJ393-8): Connects directly to the differential microphone and mono earphone channels.
3. Verified Pinout Tables: Header P1 & P2
A6A7.SchDoc).
Header P1 (Left Header — Antennas Facing Up)
| Pin | Label | Type | Voltage Domain | Description & Engineering Notes |
|---|---|---|---|---|
| 1 | EN | Input | Up to VIN | MP1584 Buck Enable. Pulled HIGH via 100kΩ. Pull LOW to disable power. |
| 2 | VCC4.0 / VBAT | Power | 3.5V – 4.2V | Module Power Rail. Output of MP1584 buck or input for direct 3.7V Li-ion battery. |
| 3 | GND | Power | 0V | System Ground. Must connect to microcontroller GND. |
| 4 | U_RXD | Input | 2.8V / 3.3V Logic | Main AT Command RX. Receives commands from MCU. Use 1k/2k divider for 5V Arduinos. |
| 5 | U_TXD | Output | 2.8V / 3.3V Logic | Main AT Command TX. Sends command responses and unsolicited notifications (+CMT, RING). |
| 6 | GND | Power | 0V | System Ground. |
| 7 | HST_TXD | Output | 2.8V / 3.3V Logic | Host/Firmware Debug TX (921,600 baud). Leave unconnected. |
| 8 | HST_RXD | Input | 2.8V / 3.3V Logic | Host/Firmware Debug RX. Leave unconnected. |
| 9 | RS232_TXD | Output | ±6V to ±10V | True RS-232 Transmit (from SP3232). For direct PC DB9 COM port connection. |
| 10 | RS232_RXD | Input | ±6V to ±10V | True RS-232 Receive (into SP3232). For direct PC DB9 COM port connection. |
| 11 | GPS_TXD | Output | 2.8V / 3.3V Logic | Dedicated GPS NMEA Output. Emits continuous NMEA stream at 9600 baud when GPS is enabled. |
| 12 | GND | Power | 0V | System Ground. |
Header P2 (Right Header — Antennas Facing Up)
| Pin | Label | Type | Voltage Domain | Description & Engineering Notes |
|---|---|---|---|---|
| 1 | REC+ | Output | Analog Audio | Differential Loudspeaker / Receiver positive terminal. |
| 2 | REC- | Output | Analog Audio | Differential Loudspeaker / Receiver negative terminal. |
| 3 | MIC+ | Input | Analog Audio | Differential Microphone positive terminal. |
| 4 | MIC- | Input | Analog Audio | Differential Microphone negative terminal. |
| 5 | RESET | Input | 2.8V / 3.3V Logic | Hardware Reset. Active LOW. Pull to GND for >100ms to trigger clean system reboot. |
| 6 | U_RTS | Output | 2.8V / 3.3V Logic | UART Hardware Flow Control RTS. Leave floating if unused. |
| 7 | U_CTS | Input | 2.8V / 3.3V Logic | UART Hardware Flow Control CTS. Leave floating if unused. |
| 8 | SLEEP | Input | 2.8V / 3.3V Logic | Low-Power Control. Drive HIGH to force sleep (<1.5mA); drive LOW to wake. |
| 9 | GND | Power | 0V | System Ground. |
| 10 | GND | Power | 0V | System Ground. |
| 11 | PWR_KEY | Input | Up to VBAT (4.0V) | Power On/Boot Trigger. Active HIGH. Connect to VBAT for 2.5s to turn module ON. |
| 12 | VCC4.0 / VBAT | Power | 3.5V – 4.2V | Module Power Rail. Electrically identical to P1 Pin 2. |
Optimal ESP32 to AI-Thinker A7 Interconnect Guide
Need to wire an ESP32 without triggering boot loops (GPIO 12 MTDI flash brownout), blocking internal PSRAM (GPIO 16/17 on WROVER), or stealing the hardware I2C & SPI buses? Discover the zero-conflict pinout using input-only GPI pins.
4. RF Antenna Ports & Onboard LEDs
Antenna Sockets (u.FL / IPEX)
GSM Port (J3): Miniature u.FL connector. Requires Quad-Band (850/900/1800/1900 MHz) omnidirectional antenna. Solder pads for an optional SMA connector (J2) are adjacent.
GPS Port (J4): Miniature u.FL connector. Crucial Note: The board provides NO DC bias voltage on this port. Active GPS antenna pucks will not work without an external bias tee mod (see Chapter 4). Use a passive patch antenna for zero-hassle operation.
Status Indicator LEDs
- D1 (Red, POWER): Solid RED when the 4.0V rail is powered by the MP1584 buck converter or battery.
- LED1 (NET): Cellular Network Status:
• Fast blink (~800ms): Searching for cellular network.
• Slow blink (~3000ms): Registered on network (Idle/Standby). - LED2 (GPS / STAT): Connected to Module GPIO6. Indicates GPS operational activity or CPU running state.